ISSN 0253-2778

CN 34-1054/N

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A variable granularity-based mapping scheme

  • School of Electronics and Information Engineering, Anhui University, Hefei 230039, China

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https://doi.org/10.3969/j.issn.0253-2778.2017.10.010
  • Received Date: 10 January 2017
  • Rev Recd Date: 03 May 2017
  • Publish Date: 31 October 2017
    Abstract

  • Abstract

    Address mapping is the most important function of flash translation layer (FTL), and it should have both high performance and low memory footprint. Although demand-based address mapping scheme(DFTL) has relatively high performance and low memory footprint, it has problems. First, it is a page-level mapping scheme. Each cache slot stores only one mapping record, and each mapping record stores only one physical page number and the corresponding logical page number, so that the cache , at a fixed size, can only store a limited number of mapping records. Second, each mapping record itself cannot exploit the spatial locality of the request. Thus, in the DFTL scheme, since the cache hit ratio is low, DFTL has to frequently access the mapping pages in the flash memory to read the mapping records, which significantly reduces the performance of the system. A new scheme named VGFTL (a mapping scheme of variable granularity-based flash translation layer) was proposed, which could significantly increase the cache hit ratio. Experimental results show that the average hit ratio of cache has reached 89.85% in VGFTL scheme, which is much higher than that of the DFTL scheme, 45.46%. VGFTL can significantly reduce the number of block erasures and system response time compared to DFTL, and is close to pure page-level mapping scheme in performance.

    Abstract

    Address mapping is the most important function of flash translation layer (FTL), and it should have both high performance and low memory footprint. Although demand-based address mapping scheme(DFTL) has relatively high performance and low memory footprint, it has problems. First, it is a page-level mapping scheme. Each cache slot stores only one mapping record, and each mapping record stores only one physical page number and the corresponding logical page number, so that the cache , at a fixed size, can only store a limited number of mapping records. Second, each mapping record itself cannot exploit the spatial locality of the request. Thus, in the DFTL scheme, since the cache hit ratio is low, DFTL has to frequently access the mapping pages in the flash memory to read the mapping records, which significantly reduces the performance of the system. A new scheme named VGFTL (a mapping scheme of variable granularity-based flash translation layer) was proposed, which could significantly increase the cache hit ratio. Experimental results show that the average hit ratio of cache has reached 89.85% in VGFTL scheme, which is much higher than that of the DFTL scheme, 45.46%. VGFTL can significantly reduce the number of block erasures and system response time compared to DFTL, and is close to pure page-level mapping scheme in performance.
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    • References(13)
  • [1]
    CHUNG T S, PARK D J, PARK S, et al. A survey of flash translation layer[J]. Journal of Systems Architecture, 2009, 55(5-6): 332-343.
    [2]
    XU G X, LIN F Y, XIAO Y P. CLRU: A new page replacement algorithm for NAND flash-based consumer electronics[J]. IEEE Transactions on Consumer Electronics, 2014, 60(1): 38-44.
    [3]
    CHOUDHURI S, GIVARGIS T. Performance improvement of block based NAND flash translation layer[C]// Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis. Salzburg,Austria: ACM, 2007: 257-262.
    [4]
    QIN Z W, WANG Y, LIU D, et al. Demand-based block-level address mapping in large-scale NAND flash storage systems[C]// Proceedings of the 8th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. Scottsdale, USA: ACM, 2010: 173-182.
    [5]
    CHO H, SHIN D, EOM Y I. KAST: K-Associative sector translation for NAND flash memory in real-time systems[C]// Proceeding of the Design, Automation & Test in Europe Conference & Exhibition. Nice, France: IEEE, 2009: 507-512.
    [6]
    GUPTA A, KIM Y, URGAONKAR B. DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings[C]// Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems. Washington, USA: ACM, 2009: 229-240.
    [7]
    XIE W, CHEN Y, ROTH P C. A low-cost adaptive data separation method for the flash translation layer of solid state drives[C]// Proceedings of the International Workshop on Data-Intensive Scalable Computing Systems. Austin, USA: ACM, 2015: No.3, 1-8.
    [8]
    ZHOU Y, WU F, HUANG P, et al. TPFTL: An efficient page-level FTL to optimize address translation in flash memory[C]// Proceedings of the 10th European Conference on Computer Systems. Bordeaux, France: ACM, 2015: No.12, 1-16.
    [9]
    WEI Q S, CHEN C, XUE M D, et al. Z-MAP: A zone-based flash translation layer with workload classification for solid-state drive[J]. ACM Transactions on Storage, 2015, 11(1): No.4, 1-33.
    [10]
    BUCY J S, GANGER G R. The DiskSim simulation environment version 3.0 reference manual[BE/OL]. [2017-10-18], http://www.pdl.cmu.edu/DiskSim/.
    [11]
    A simulator for various FTL schemes[BE/OL]. Department of Computer Science and Engineering, Pennsylvania State University, [2017-10-18], http://csl.cse.psu.edu/?q=node/322.
    [12]
    Websearch trace and OLTP trace from umass trace repository[BE/OL]. [2017-10-18], http://traces.cs.umass.edu/index.php/Storage/Storage.
    [13]
    Block traces from SNIA[BE/OL]. [2017-10-18],http://iotta.snia.org/traces/list/BlockIO.
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    [1]
    CHUNG T S, PARK D J, PARK S, et al. A survey of flash translation layer[J]. Journal of Systems Architecture, 2009, 55(5-6): 332-343.
    [2]
    XU G X, LIN F Y, XIAO Y P. CLRU: A new page replacement algorithm for NAND flash-based consumer electronics[J]. IEEE Transactions on Consumer Electronics, 2014, 60(1): 38-44.
    [3]
    CHOUDHURI S, GIVARGIS T. Performance improvement of block based NAND flash translation layer[C]// Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis. Salzburg,Austria: ACM, 2007: 257-262.
    [4]
    QIN Z W, WANG Y, LIU D, et al. Demand-based block-level address mapping in large-scale NAND flash storage systems[C]// Proceedings of the 8th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. Scottsdale, USA: ACM, 2010: 173-182.
    [5]
    CHO H, SHIN D, EOM Y I. KAST: K-Associative sector translation for NAND flash memory in real-time systems[C]// Proceeding of the Design, Automation & Test in Europe Conference & Exhibition. Nice, France: IEEE, 2009: 507-512.
    [6]
    GUPTA A, KIM Y, URGAONKAR B. DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings[C]// Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems. Washington, USA: ACM, 2009: 229-240.
    [7]
    XIE W, CHEN Y, ROTH P C. A low-cost adaptive data separation method for the flash translation layer of solid state drives[C]// Proceedings of the International Workshop on Data-Intensive Scalable Computing Systems. Austin, USA: ACM, 2015: No.3, 1-8.
    [8]
    ZHOU Y, WU F, HUANG P, et al. TPFTL: An efficient page-level FTL to optimize address translation in flash memory[C]// Proceedings of the 10th European Conference on Computer Systems. Bordeaux, France: ACM, 2015: No.12, 1-16.
    [9]
    WEI Q S, CHEN C, XUE M D, et al. Z-MAP: A zone-based flash translation layer with workload classification for solid-state drive[J]. ACM Transactions on Storage, 2015, 11(1): No.4, 1-33.
    [10]
    BUCY J S, GANGER G R. The DiskSim simulation environment version 3.0 reference manual[BE/OL]. [2017-10-18], http://www.pdl.cmu.edu/DiskSim/.
    [11]
    A simulator for various FTL schemes[BE/OL]. Department of Computer Science and Engineering, Pennsylvania State University, [2017-10-18], http://csl.cse.psu.edu/?q=node/322.
    [12]
    Websearch trace and OLTP trace from umass trace repository[BE/OL]. [2017-10-18], http://traces.cs.umass.edu/index.php/Storage/Storage.
    [13]
    Block traces from SNIA[BE/OL]. [2017-10-18],http://iotta.snia.org/traces/list/BlockIO.
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