ISSN 0253-2778

CN 34-1054/N

Open AccessOpen Access JUSTC Original Paper

Design of multiple pointer elastic buffer for high-speed interface

Cite this:
https://doi.org/10.3969/j.issn.0253-2778.2017.10.008
  • Received Date: 13 April 2016
  • Rev Recd Date: 10 January 2017
  • Publish Date: 31 October 2017
  • Elastic buffers are widely used in the high speed interface of the physical layer, which usually completes the addition and deletion of skip(SKP) by reading/writing pointer jumping and breakpoint preservation. However, common single pointer elastic buffer must be operated at high frequencies, which would make it easy to create complex timing problems. To solve these problems, based on the FPGA and the USB3.0 protocol, a four read/write pointer addressing elastic buffer to complete the addition and deletion of SKP has been proposed. First, the elastic buffer makes use of the input control unit to change the sequence of the SKP pairs in the input data and the output control unit to change the output data. Then, the threshold detection unit sends the valid instructions to the read/write pointer control unit by checking whether the amount of valid data in the elastic buffer achieves the threshold which is added or deleted. Last, to maintain the elastic buffer in half full state, the SKP in data is added or deleted by controlling the addressing of the four read/write pointers. Experimental results show that the designed elastic buffer can achieve the function of SKP addition and deletion, and its clock frequency can satisfy the protocol of Universal Serial Bus 3.0.
    Elastic buffers are widely used in the high speed interface of the physical layer, which usually completes the addition and deletion of skip(SKP) by reading/writing pointer jumping and breakpoint preservation. However, common single pointer elastic buffer must be operated at high frequencies, which would make it easy to create complex timing problems. To solve these problems, based on the FPGA and the USB3.0 protocol, a four read/write pointer addressing elastic buffer to complete the addition and deletion of SKP has been proposed. First, the elastic buffer makes use of the input control unit to change the sequence of the SKP pairs in the input data and the output control unit to change the output data. Then, the threshold detection unit sends the valid instructions to the read/write pointer control unit by checking whether the amount of valid data in the elastic buffer achieves the threshold which is added or deleted. Last, to maintain the elastic buffer in half full state, the SKP in data is added or deleted by controlling the addressing of the four read/write pointers. Experimental results show that the designed elastic buffer can achieve the function of SKP addition and deletion, and its clock frequency can satisfy the protocol of Universal Serial Bus 3.0.
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  • [1]
    WINKLES J. Elastic buffer implementations in PCI express devices[EB/OL]. [2017-10-18], http://www.doc88.com/p-781379861436.html, Mindshare Inc.
    [2]
    彭琰, 曾云, 王太宏,等. 基于HID类USB外设功能控制器的ASIC设计[J]. 微电子学与计算机, 2009, 26(4): 15-18.
    [3]
    Wikipedia. USB[EB/OL].[2011-09-28], http://en.wikipedia.org.
    [4]
    朱小明, 王小力, 程曾. USB3.0物理层中弹性缓冲器的设计与实现[J]. 微电子学与计算机, 2012, 29(6): 117-121.
    [5]
    邢辉. 弹性缓冲在USB3.0物理层中设计与实现[EB/OL]. 北京: 中国科技论文在线, 2012.
    [6]
    廖艳,王广君,高杨. FPGA异步时钟设计中的同步策略[J].自动化技术与应用, 2006, 25(1): 67-68.
    [7]
    Universal Serial Bus 3.0 Specification. 112009004327.5[P]. USA:HP Company, 2008.
    [8]
    郑乾, 晏敏, 赵建中,等. 基于PCIE2.0的物理层弹性缓冲器设计[J]. 计算机工程, 2014, 40(10): 71-75.
    [9]
    MICHELOGIANNAKIS G, BALFOUR J, DALLY W J. Elastic buffer flow control for On-chip Network[C]// The 15th International Symposium on High Performance Computer Architecture. Raleigh, USA: IEEE, 2009: 151-162.
    [10]
    刘奇浩, 翁慧辉, 张峰,等.65nm工艺下基于PCI Express2.0 协议的物理层编码子层设计[J].中国集成电路, 2013, 22(3): 41-45.
    [11]
    WOODRAL D E. Elastic buffer module for PCI express devoices, 7281077B2 [P]. USA, 2007.
    [12]
    CUMMINGS C E. Simulation and synthesis techniques for as synchronous FIFO design with asynchronous pointer comparisons [EB/OL]. [2017-10-18], http://read.pudn.com/downloads116/doc/495591/asyn_FIFO.pdf.
    [13]
    郑争兵. 基于FPGA的高速采样缓存系统的设计与实现[J]. 计算机应用, 2012, 32(11): 3259-3261.
  • 加载中

Catalog

    [1]
    WINKLES J. Elastic buffer implementations in PCI express devices[EB/OL]. [2017-10-18], http://www.doc88.com/p-781379861436.html, Mindshare Inc.
    [2]
    彭琰, 曾云, 王太宏,等. 基于HID类USB外设功能控制器的ASIC设计[J]. 微电子学与计算机, 2009, 26(4): 15-18.
    [3]
    Wikipedia. USB[EB/OL].[2011-09-28], http://en.wikipedia.org.
    [4]
    朱小明, 王小力, 程曾. USB3.0物理层中弹性缓冲器的设计与实现[J]. 微电子学与计算机, 2012, 29(6): 117-121.
    [5]
    邢辉. 弹性缓冲在USB3.0物理层中设计与实现[EB/OL]. 北京: 中国科技论文在线, 2012.
    [6]
    廖艳,王广君,高杨. FPGA异步时钟设计中的同步策略[J].自动化技术与应用, 2006, 25(1): 67-68.
    [7]
    Universal Serial Bus 3.0 Specification. 112009004327.5[P]. USA:HP Company, 2008.
    [8]
    郑乾, 晏敏, 赵建中,等. 基于PCIE2.0的物理层弹性缓冲器设计[J]. 计算机工程, 2014, 40(10): 71-75.
    [9]
    MICHELOGIANNAKIS G, BALFOUR J, DALLY W J. Elastic buffer flow control for On-chip Network[C]// The 15th International Symposium on High Performance Computer Architecture. Raleigh, USA: IEEE, 2009: 151-162.
    [10]
    刘奇浩, 翁慧辉, 张峰,等.65nm工艺下基于PCI Express2.0 协议的物理层编码子层设计[J].中国集成电路, 2013, 22(3): 41-45.
    [11]
    WOODRAL D E. Elastic buffer module for PCI express devoices, 7281077B2 [P]. USA, 2007.
    [12]
    CUMMINGS C E. Simulation and synthesis techniques for as synchronous FIFO design with asynchronous pointer comparisons [EB/OL]. [2017-10-18], http://read.pudn.com/downloads116/doc/495591/asyn_FIFO.pdf.
    [13]
    郑争兵. 基于FPGA的高速采样缓存系统的设计与实现[J]. 计算机应用, 2012, 32(11): 3259-3261.

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